AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 949
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 949 of 1218
- Download datasheet (19Mb)
40.10.3
6438F–ATARM–21-Jun-10
Interleaved Mode
The vertical position can be easily calculated by dividing the data at offset 2 (X
at offset 3(Y
The horizontal position can be easily calculated by dividing the data at offset 5 (Y
data at offset 7 (X
The Pressure measure can be calculated using the following formula
Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1]
In the Interleaved Mode, the conversion of the touch screen channels are made in parallel to
each channel. In addition to interleaving, the analog channels 4 and 5 can be converted more
often than the touch screen channels depending on the TSFREQ field in the register
TSADCC_MR. In the interleaved mode at least one ADC channel must be enabled.
In the Interleaved Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are auto-
matically activated and the bits CH0 to CH3 are automatically set in the
Status
This mode allows periodic conversion of the remaining channels at high sampling rate and con-
verted data transferred in memory with the PDC while the touch screen conversions are
performed at low rate. The PDC transfers only analog channel data and touch screen data must
be read in the
The resolution can be configured for the channel 4 to
olution for the conversion made on channels 0 to 3 is forced to 10 bits.
At each trigger, the sequence performed depends on a Trigger Counter, which is compared at
the end to the Touch Screen Frequency, as defined by the field TSFREQ in the register
TSADCC_MR:
unless TSFREQ is programmed at 0 or 1. In such cases, the Touch Screen Frequency is one-
sixth of the Trigger Frequency.
As TSFREQ varies between 0 and 15, this results in the ADC channels being converted
between 6 to 65536 less often than the Touch Screen channels.
If the bit PRES in
are as follow:
7. X
8. AD4 to AD7 if enabled.
• For Trigger Counter at 0:
1. Close the switches on the inputs X
2. Convert Channel X
3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corre-
4. Set Trigger Counter to 1.
sponding TSADCC_CDRx and TSADCC_LCDR.
Touch Screen Frequency = Trigger Frequency / (2
Register”.
P
- Y
M
P
- X
“TSADCC Channel Data Register x (x =
M
P
).
“TSADCC Mode Register”
- Y
M
).
M
and store the result in TSADCC_CDR1.
P
and X
is disabled (measure only position), the sequences
M
during the Sample and Hold Time.
7
0..7)”.
only, through the LOWRES bit. The res-
TSFREQ+1
)
AT91SAM9G45
“TSADCC Channel
P
- X
M
P
) by the data
- Y
M
) by the
949
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