AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 847

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

38.5.9
38.5.10
38.5.11
847
AT91SAM9G45
Speed Identification
USB V2.0 High Speed Global Interrupt
Endpoint Interrupts
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high
speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of
the device.
Interrupts are defined in
in
Interrupts are enabled in UDPHS_IEN (see
and individually masked in UDPHS_EPTCTLENBx (see
Control Enable
.
Table 38-4.
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ERR_CRISO/ERR_NB_TRA
RX_SETUP/ERR_FL_ISO
TX_PK_RD /ERR_TRANS
TX_COMPLT
RX_BK_RDY
ERR_OVFLW
MDATA_RX
DATAX_RX
Section 38.6.4 ”UDPHS Interrupt Status Register”
Endpoint Interrupt Source Masks
Register”).
Section 38.6.3 ”UDPHS Interrupt Enable Register”
Section 38.6.3 ”UDPHS Interrupt Enable
Short Packet Interrupt
Busy Bank Interrupt
NAKOUT Interrupt
NAKIN/Error Flush Interrupt
Stall Sent/CRC error/Number of Transaction
Error Interrupt
Received SETUP/Error Flow Interrupt
TX Packet Read/Transaction Error Interrupt
Transmitted IN Data Complete Interrupt
Received OUT Data Interrupt
Overflow Error Interrupt
MDATA Interrupt
DATAx Interrupt
(UDPHS_INTSTA).
Section 38.6.12 ”UDPHS Endpoint
6438F–ATARM–21-Jun-10
(UDPHS_IEN) and
Register”)