IPR-NIOS Altera, IPR-NIOS Datasheet - Page 112

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–4
Nios II Processor Reference Handbook
General Exception Vector
Memory Management Unit Settings
f
1
For details on reset exceptions, refer to the
Processor Reference Handbook.
You can select the memory module where the general exception vector (exception
address) resides, and the location of the general exception vector. The general
exception vector cannot be configured until your system memory components are in
place.
The Memory list, which includes all memory modules mastered by the Nios II
processor, allows you to select the exception vector memory module. In a typical
system, you select a low-latency memory module for the exception code.
Offset allows you to specify the location of the exception vector relative to the
memory module’s base address. SOPC Builder calculates the physical address of the
exception vector when you modify the memory module, the offset, or the memory
module’s base address. This address, displayed next to the Offset box, is always a
physical address, even when an MMU is present.
For details on exceptions, refer to the
Processor Reference Handbook.
The Nios II/f core offers a memory management unit (MMU) to support full-featured
operating systems. Turning on Include MMU includes the Nios II MMU in your
Nios II hardware system.
Do not include an MMU in your Nios II system unless your operating system requires
it. The MMU is only useful with software that takes advantage of it. Many Nios II
systems involve simpler system software, such as Altera
Such software is unlikely to function correctly with an MMU-based Nios II processor.
Fast TLB Miss Exception Vector
The fast TLB miss exception vector is a special exception vector used exclusively by
the MMU to handle TLB miss exceptions. You can select the memory module where
the fast TLB miss exception vector (exception address) resides, and the location of the
fast TLB miss exception vector. The fast TLB miss exception vector cannot be
configured until your system memory components are in place.
The Memory list, which includes all memory modules mastered by the Nios II
processor, allows you to select the exception vector memory module. In a typical
system, you select a low-latency memory module for the exception code.
Offset allows you to specify the location of the exception vector relative to the
memory module’s base address. SOPC Builder calculates the physical address of the
exception vector when you modify the memory module, the offset, or the memory
module’s base address. This address, displayed next to the Offset box, is always a
physical address.
Programming Model
Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Programming Model
®
chapter of the Nios II
HAL or MicroC/OS-II.
December 2010 Altera Corporation
chapter of the Nios II
Core Nios II Page