IPR-NIOS Altera, IPR-NIOS Datasheet - Page 145

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/f Core
Table 5–10. Instruction Execution Performance for Nios II/f Core 4byte/line data cache (Part 2 of 2)
December 2010 Altera Corporation
Shift/rotate (without hardware multiply present)
All other instructions
Note to
(1) Depends on the hardware multiply or divide option. Refer to
(2) In the default Nios II/f configuration, these instructions require four clock cycles. If any of the following options are present, they require five
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■
■
■
■
■
■
clock cycles:
MMU
MPU
Division exception
Misaligned load/store address exception
Extra exception information
EIC port
Shadow register sets
Table
Exception Handling
5–10:
The Nios II/f core supports the following exception types:
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■
■
■
■
■
■
■
■
■
■
■
■
■
External Interrupt Controller Interface
The EIC interface enables you to speed up interrupt handling in a complex system by
adding a custom interrupt controller.
The EIC interface is an Avalon-ST sink with the following input signals:
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■
Signals are rising-edge triggered, and synchronized with the Nios II clock input.
Hardware interrupts
Software trap
Illegal instruction
Unimplemented instruction
Supervisor-only instruction (MMU or MPU only)
Supervisor-only instruction address (MMU or MPU only)
Supervisor-only data address (MMU or MPU only)
Misaligned data address
Misaligned destination address
Division error
Fast translation lookaside buffer (TLB) miss (MMU only)
Double TLB miss (MMU only)
TLB permission violation (MMU only)
MPU region violation (MPU only)
eic_port_valid
eic_port_data
Instruction
Table 5–4 on page 5–6
for details.
Nios II Processor Reference Handbook
Cycles
1—32
1
Late result
Penalties
5–13