IPR-NIOS Altera, IPR-NIOS Datasheet - Page 59

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–8. status Control Register Field Descriptions (Part 2 of 3)
December 2010 Altera Corporation
PRS
CRS
IL
IH
EH
U
Bit
(2)
(2)
PRS is the previous register set field. The processor copies the CRS field to
the PRS field upon one of the following events:
■
■
The processor copies CRS to PRS immediately after copying the status
register to estatus, bstatus or sstatus.
The number of significant bits in the CRS and PRS fields depends on the
number of shadow register sets implemented in the Nios II core. The value
of CRS and PRS can range from 0 to n-1, where n is the number of
implemented register sets. The processor core implements the number of
significant bits needed to represent n-1. Unused high-order bits are always
read as 0, and must be written as 0.
1
the PRS field. Processor behavior is undefined with an unimplemented
register set number.
CRS is the current register set field. CRS indicates which register set is
currently in use. Register set 0 is the normal register set, while register sets
1 and higher are shadow register sets. The processor sets CRS to zero on
any noninterrupt exception.
The number of significant bits in the CRS and PRS fields depends on the
number of shadow register sets implemented in the Nios II core. Unused
high-order bits are always read as 0, and must be written as 0.
IL is the interrupt level field. The IL field controls what level of external
maskable interrupts can be serviced. The processor services a maskable
interrupt only if its requested interrupt level is greater than IL.
IH is the interrupt handler mode bit. The processor sets IH to one when it
takes an external interrupt.
EH is the exception handler mode bit. The processor sets EH to one when an
exception occurs (including breaks). Software clears EH to zero when ready
to handle exceptions again. EH is used by the MMU to determine whether a
TLB miss exception is a fast TLB miss or a double TLB miss. In systems
without an MMU, EH is always zero.
U is the user mode bit. When U = 1, the processor operates in user mode.
When U = 0, the processor operates in supervisor mode. In systems without
an MMU, U is always zero.
In a processor with no MMU, on any exception
In a processor with an MMU, on one of the following:
■
■
Ensure that system software writes only valid register set numbers to
Break exception
Nonbreak exception when status.EH is zero
Description
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Access
Nios II Processor Reference Handbook
(1)
Reset
0
0
0
0
0
0
MMU only
Available
MPU only
sets only
sets only
interface
only
interface
only
Shadow
Shadow
MMU or
register
register
EIC
EIC
(3)
(3)
(3)
(3)
(3)
(3)
3–13