IPR-NIOS Altera, IPR-NIOS Datasheet - Page 99

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Memory and Peripheral Access
Memory and Peripheral Access
December 2010 Altera Corporation
Cache Memory
f
Interrupt Levels
The status.IL field controls what level of external maskable interrupts can be
serviced. The processor services a maskable interrupt only if its requested interrupt
level is greater than status.IL.
An ISR can make run-time adjustments to interrupt nesting by manipulating
status.IL. For example, if an ISR is running at level 5, to temporarily allow
pre-emption by another level 5 interrupt, it can set status.IL to 4.
To enable all external interrupts, set status.IL to 0. To disable all external interrupts,
set status.IL to 63.
Masking Interrupts with the Internal Interrupt Controller
The ienable register controls the handling of internal hardware interrupts. Each bit of
the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A
value of one in bit n means that the corresponding irqn interrupt is enabled; a bit
value of zero means that the corresponding interrupt is disabled. Refer to
Processing” on page 3–30
An ISR can adjust ienable so that IRQs of equal or lower priority are disabled. Refer
to
Nios II addresses are 32 bits, allowing access up to a 4-gigabyte address space. Nios II
core implementations without MMUs restrict addresses to 31 bits or fewer. The MMU
supports the full 32-bit physical address.
For details, refer to the
Processor Reference Handbook.
Peripherals, data memory, and program memory are mapped into the same address
space. The locations of memory and peripherals within the address space are
determined at system generation time. Reading or writing to an address that does not
map to a memory or peripheral produces an undefined result.
The processor’s data bus is 32 bits wide. Instructions are available to read and write
byte, half-word (16-bit), or word (32-bit) data.
The Nios II architecture is little endian. For data wider than 8 bits stored in memory,
the more-significant bits are located in higher addresses.
The Nios II architecture supports register+immediate addressing.
The Nios II architecture and instruction set accommodate the presence of data cache
and instruction cache memories. Cache management is implemented in software by
using cache management instructions. Instructions are provided to initialize the
cache, flush the caches whenever necessary, and to bypass the data cache to properly
access memory-mapped peripherals.
The Nios II architecture provides the following mechanisms to bypass the cache:
“Handling Nested Exceptions” on page 3–48
Nios II Core Implementation Details
for more information.
for more information.
chapter of the Nios II
Nios II Processor Reference Handbook
“Exception
3–53