IPR-NIOS Altera, IPR-NIOS Datasheet - Page 56

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–10
Registers
Table 3–5. The Nios II General-purpose Registers (Part 1 of 2)
Nios II Processor Reference Handbook
r0
r1
r2
r3
Register
Overlapping Regions
Enabling the MPU
General-purpose Registers
zero
at
Name
Default Cacheability
The default cacheability specifies whether normal load and store instructions access
the data cache or bypass the data cache. The default cacheability is only present for
data regions. You can override the default cacheability by using the ldio or stio
instructions. The bit 31 cache bypass feature is available when the MPU is present.
Refer to
The memory addresses of regions can overlap. Overlapping regions have several uses
including placing markers or small holes inside of a larger region. For example, the
stack and heap may be located in the same region, growing from opposite ends of the
address range. To detect stack/heap overflows, you can define a small region between
the stack and heap with no access permissions and assign it a higher priority than the
larger region. Any access attempts to the hole region trigger an exception informing
system software about the stack/heap overflow.
If regions overlap so that a particular access matches more than one region, the region
with the highest priority (lowest index) determines the access permissions and default
cacheability.
The MPU is disabled on system reset. System software enables and disables the MPU
by writing to a control register. Before enabling the MPU, you must create at least one
instruction and one data region, otherwise unexpected results can occur. Refer to
“Working with the MPU” on page 3–29
The Nios II register set includes general-purpose registers and control registers. In
addition, the Nios II/f core can optionally have shadow register sets. This section
discusses each register type.
The Nios II architecture provides thirty-two 32-bit general-purpose registers, r0
through r31, as shown in
assembler. For example, the zero register (r0) always returns the value zero, and
writing to zero has no effect. The ra register (r31) holds the return address used by
procedure calls and is implicitly accessed by the call, callr and ret instructions. C
and C++ compilers use a common procedure-call convention, assigning specific
meaning to registers r1 through r23 and r26 through r28.
0x00000000
Assembler temporary
Return value
Return value
“Cache Memory” on page 3–53
Function
Table
3–5. Some registers have names recognized by the
r16
r17
r18
r19
Register
for more information.
for more information on cache bypass.
Name
Callee-saved register
Callee-saved register
Callee-saved register
Callee-saved register
December 2010 Altera Corporation
Chapter 3: Programming Model
Function
Registers