IPR-NIOS Altera, IPR-NIOS Datasheet - Page 115

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Caches and Memory Interfaces Page
Figure 4–2. Caches and Memory Interfaces Page in the Nios II Processor Parameter Editor
December 2010 Altera Corporation
Data Master Settings
■
The Data Master settings provide the following options for the Nios II/f core:
■
Include tightly coupled instruction master port(s)—When on, the Nios II
processor includes tightly-coupled memory ports. You can specify one to four
ports with the Number of ports setting. Tightly-coupled memory ports appear on
the connection panel of the Nios II processor in the SOPC Builder System
Contents tab. You must connect each port to exactly one memory component in
the system.
Data Cache—Specifies the size of the data cache. Valid sizes are from 512 bytes to
64 KBytes, or None. Depending on the value specified for Data Cache, the
following options are available:
■
■
Data Cache Line Size—Valid sizes are 4 bytes, 16 bytes, or 32 bytes.
Omit data master port—If you set Data Cache to None, you can optionally
turn on Omit data master port to remove the Avalon-MM data master port
from the Nios II processor. In this case, you must include a tightly-coupled data
memory.
Nios II Processor Reference Handbook
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