IPR-NIOS Altera, IPR-NIOS Datasheet - Page 97

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
Handling Nonmaskable Interrupts
Returning From Interrupt and Instruction-Related Exceptions
1
1
1
System software can globally disable fast nested interrupts by setting config.ANI to 0.
In this state, the Nios II processor disables interrupts when taking a maskable
interrupt (nonmaskable interrupts always disable maskable interrupts). Individual
ISRs can re-enable nested interrupts by setting status.PIE to 1, as described in
“Nested Exceptions with the Internal Interrupt Controller” on page
Writing an NMI handler involves the same basic techniques as writing any other
interrupt handler. However, nonmaskable interrupts always pre-empt maskable
interrupts, and cannot be pre-empted. This can simplify handler design in some ways,
but it means that an NMI handler can have a significant impact on overall interrupt
latency. For the best system performance, perform the absolute minimum of
processing in your NMI handlers, and defer less-critical processing to maskable
interrupt handlers or foreground software.
NMIs leave intact the processor state associated with maskable interrupts and other
exceptions, as well as normal, nonexception processing, provided each NMI is
assigned to a dedicated shadow register set. Therefore NMIs can be handled
transparently.
If not assigned to a dedicated shadow register set, an NMI can overwrite the
processor status associated with exception processing, making it impossible to return
to the interrupted exception.
Do not set status.PIE in a nonmaskable ISR. If status.PIE is set, a maskable
interrupt can pre-empt an NMI, and the processor exits NMI mode. It cannot be
returned to NMI mode until the next nonmaskable interrupt.
The eret instruction is used to resume execution at the pre-exception address.
You must ensure that when an exception handler modifies registers, they are restored
when it returns. This can be taken care of in either of the following ways:
■
■
It is not necessary to save and restore the exception temporary (et or r24) register.
When executing the eret instruction, the processor performs the following tasks:
In the case of ISRs, if the EIC interface and shadow register sets are implemented,
and the ISR has a dedicated register set, no software action is required. The Nios II
processor returns to the previous register set when it executes eret, which restores
the register contents. For details, refer to
Interrupt
In the case of noninterrupt exceptions, for ISRs in a system with the internal
interrupt controller, and for ISRs without a dedicated shadow register set, the
exception handler must save registers on entry and restore them on exit. Saving
the register contents on the stack is a typical, re-entrant implementation.
Controller”.
“Nested Exceptions with an External
Nios II Processor Reference Handbook
3–49.
3–51