IPR-NIOS Altera, IPR-NIOS Datasheet - Page 135

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Device Family Support
Table 5–1. Nios II Processor Cores (Part 3 of 3)
Device Family Support
December 2010 Altera Corporation
Exception
Handling
Shadow Register Sets
User Mode Support
Custom Instruction Support
Notes to
(1) DMIPS performance for the Nios II/s and Nios II/f cores depends on the hardware multiply option.
(2) Using the fastest hardware multiply option, and targeting a Stratix
(3) Multiply and shift performance depends on the hardware multiply option you use. If no hardware multiply option is used, multiply operations
are emulated in software, and shift operations require one cycle per bit. For details, refer to the arithmetic logic unit description for each core.
Table
5–1:
Exception Types
Integrated Interrupt
Controller
External Interrupt Controller
Interface
Feature
All Nios II cores provide the same support for target Altera
cores provide device family support to each of the Altera device families as shown in
Table
Table 5–2. Device Family Support (Part 1 of 2)
5–2.
Device Family
Cyclone III LS
Cyclone
Cyclone III
Arria II GX
Arria
®
Yes
Software trap,
unimplemented
instruction, illegal
instruction, hardware
interrupt
Yes
No
No
No; Permanently in
supervisor mode
GX
®
II
Nios II/e
®
II FPGA in the fastest speed grade.
Software trap,
unimplemented
instruction, illegal
instruction, hardware
interrupt
Yes
No
No
No; Permanently in
supervisor mode
Yes
Nios II/s
Core
Support
Preliminary
Preliminary
Nios II Processor Reference Handbook
®
Final
Final
Final
device families. Nios II
Software trap,
unimplemented
instruction, illegal
instruction,
supervisor-only
instruction,
supervisor-only instruction
address, supervisor-only
data address, misaligned
destination address,
misaligned data address,
division error, fast TLB
miss, double TLB miss,
TLB permission violation,
MPU region violation,
internal hardware interrupt,
external hardware
interrupt, nonmaskable
interrupt
Yes
Optional
Optional, up to 63
Yes; When MMU or MPU
present
Yes
(1)
Nios II/f
5–3