IPR-NIOS Altera, IPR-NIOS Datasheet - Page 122

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–14
JTAG Debug Module Page
Table 4–1. Debug Configuration Features
Nios II Processor Reference Handbook
JTAG Target Connection
Download Software
Software Breakpoints
Hardware Breakpoints
Data Triggers
Instruction Trace
Data Trace
On-Chip Trace
Off-Chip Trace
Feature
f
For details on the MPU, refer to the
Reference Handbook. For specifics on the Nios II/f core, refer to the
Implementation Details
The JTAG Debug Module page presents settings for configuring the JTAG debug
module on the Nios II processor. You can select the debug features appropriate for
your target application.
Soft-core processors such as the Nios II processor offer unique debug capabilities
beyond the features of traditional fixed processors. The soft-core nature of the Nios II
processor allows you to debug a system in development using a full-featured debug
core, and later remove the debug features to conserve logic resources. For the release
version of a product, you might choose to reduce the JTAG debug module
functionality, or remove it altogether.
Table 4–1
The following sections describe the configuration settings available.
Connects to the processor through the standard JTAG pins on the Altera FPGA. This provides the
basic capabilities to start and stop the processor, and examine/edit registers and memory.
Downloads executable code to the processor’s memory via the JTAG connection.
Sets a breakpoint on instructions residing in RAM.
Sets a breakpoint on instructions residing in nonvolatile memory, such as flash memory.
Triggers based on address value, data value, or read or write cycle. You can use a trigger to halt
the processor on specific events or conditions, or to activate other events, such as starting
execution trace, or sending a trigger signal to an external logic analyzer. Two data triggers can be
combined to form a trigger that activates on a range of data or addresses.
Captures the sequence of instructions executing on the processor in real time.
Captures the addresses and data associated with read and write operations executed by the
processor in real time.
Stores trace data in on-chip memory.
Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside the Nios II
core. Off-chip trace requires a debug probe from First Silicon Solutions (FS2) or Lauterbach
GmbH.
describes the debug features available to you for debugging your system.
chapter of the Nios II Processor Reference Handbook.
Programming Model
Description
Chapter 4: Instantiating the Nios II Processor in SOPC Builder
chapter of the Nios II Processor
December 2010 Altera Corporation
Nios II Core
JTAG Debug Module Page