IPR-NIOS Altera, IPR-NIOS Datasheet - Page 33

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
Memory and I/O Organization
Memory and I/O Organization
December 2010 Altera Corporation
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This section explains hardware implementation details of the Nios II memory and
I/O organization. The discussion covers both general concepts true of all Nios II
processor systems, as well as features that might change from system to system.
The flexible nature of the Nios II memory and I/O organization are the most notable
difference between Nios II processor systems and traditional microcontrollers.
Because Nios II processor systems are configurable, the memories and peripherals
vary from system to system. As a result, the memory and I/O organization varies
from system to system.
A Nios II core uses one or more of the following to provide memory and I/O access:
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The Nios II architecture hides the hardware details from the programmer, so
programmers can develop Nios II applications without specific knowledge of the
hardware implementation.
For details that affect programming issues, refer to the
the Nios II Processor Reference Handbook.
Instruction master port—An Avalon
that connects to instruction memory via system interconnect fabric
Instruction cache—Fast cache memory internal to the Nios II core
Data master port—An Avalon-MM master port that connects to data memory and
peripherals via system interconnect fabric
Data cache—Fast cache memory internal to the Nios II core
Tightly-coupled instruction or data memory port—Interface to fast on-chip
memory outside the Nios II core
®
Memory-Mapped (Avalon-MM) master port
Programming Model
Nios II Processor Reference Handbook
chapter of
2–11