IPR-NIOS Altera, IPR-NIOS Datasheet - Page 124

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–16
Table 4–2. JTAG Debug Module Levels (Part 2 of 2)
Nios II Processor Reference Handbook
External I/O Pins Required
JTAG Target Connection
Download Software
Software Breakpoints
Hardware Execution
Breakpoints
Data Triggers
On-Chip Trace
Off-Chip Trace
Notes to
(1) Level 4 requires the purchase of a software upgrade from FS2 or Lauterbach.
(2) Not including the dedicated JTAG pins on the Altera FPGA.
(3) An additional license from FS2 is required to use more than 16 frames.
(4) Off-chip trace requires the purchase of additional hardware from FS2 or Lauterbach.
(2)
Debug Feature
Table
Debug Signals
Break Vector
Advanced Debug Settings
4–2:
f
1
(4)
The Include debugreq and debugack signals debug signals setting provides the
following functionality. When on, the Nios II processor includes debug request and
acknowledge signals. These signals let another device temporarily suspend the
Nios II processor for debug purposes. The signals are exported to the top level of your
SOPC Builder system.
For further details on the debug signals, refer to the
the Nios II Processor Reference Handbook.
If the Nios II processor contains a JTAG debug module, SOPC Builder determines a
break vector (break address). Memory is always the processor core you are
configuring. Offset is fixed at 0x20. SOPC Builder calculates the physical address of
the break vector from the memory module’s base address and the offset.
Debug levels 3 and 4 support trace data collection into an on-chip memory buffer. You
can set the on-chip trace buffer size to sizes from 128 to 64K trace frames, using OCI
Onchip Trace. Larger buffer sizes consume more on-chip M4K RAM blocks. Every
M4K RAM block can store up to 128 trace frames.
The Nios II MMU does not support the JTAG debug module trace.
No Debug
None
No
No
0
0
0
0
0
Unlimited
Level 1
None
None
None
None
Yes
Yes
0
Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Unlimited
Level 2
None
None
Yes
Yes
0
2
2
Up to 64K Frames
Processor Architecture
Unlimited
Level 3
None
Yes
Yes
(3)
0
2
2
December 2010 Altera Corporation
JTAG Debug Module Page
Up to 64K Frames
128K Frames
Level 4
Unlimited
chapter of
Yes
Yes
20
4
4
(1)