IPR-NIOS Altera, IPR-NIOS Datasheet - Page 134

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–2
Table 5–1. Nios II Processor Cores (Part 2 of 3)
Nios II Processor Reference Handbook
External Address Space
Instruction
Bus
Data Bus
Arithmetic
Logic Unit
JTAG Debug
Module
Memory Management Unit
Memory Protection Unit
Cache
Pipelined Memory Access
Branch Prediction
Tightly-Coupled Memory
Cache
Pipelined Memory Access
Cache Bypass Methods
Tightly-Coupled Memory
Hardware Multiply
Hardware Divide
Shifter
JTAG interface, run control,
software breakpoints
Hardware Breakpoints
Off-Chip Trace Buffer
Feature
–
–
2 GB
1 cycle-per-bit
Optional
Nios II/e
–
–
–
–
–
–
–
–
–
–
–
–
2 GB
512 bytes to 64 KB
Yes
Static
Optional
3-cycle
3-cycle shift
Optional
Optional
Optional
–
–
Nios II/s
Optional
(3)
–
–
–
–
Chapter 5: Nios II Core Implementation Details
Core
(3)
December 2010 Altera Corporation
2 GB without MMU
4 GB with MMU
512 bytes to 64 KB
Yes
Dynamic
Optional
512 bytes to 64 KB
■
■
■
Optional
1-cycle
Optional
1-cycle barrel
shifter
Optional
Optional
Optional
Optional
Optional
I/O instructions
Bit-31 cache bypass
Optional MMU
(3)
(3)
Nios II/f
–
Introduction