IPR-NIOS Altera, IPR-NIOS Datasheet - Page 74

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–28
Table 3–32. sstatus Control Register Field Descriptions (Part 2 of 2)
Nios II Processor Reference Handbook
CRS
IL
IH
EH
U
PIE
Note to
(1) Refer to
(2) If the EIC interface and shadow register sets are not present SRS always reads as 0, and the processor behaves accordingly.
Bit
Table
Table 3–8 on page
3–32:
f
The sstatus register is present in the Nios II core if both the EIC interface and shadow
register sets are implemented. There is one copy of sstatus for each shadow register
set.
When the Nios II processor takes an interrupt, if a shadow register set is requested
(RRS = 0) and the MMU is not in exception handler mode (status.EH = 0), the
processor copies status to sstatus.
For details about RRS, refer to
about status.EH, refer to
Changing Register Sets
Modifying status.CRS immediately switches the Nios II processor to another register
set. However, software cannot write to status.CRS directly. To modify status.CRS,
insert the desired value into the saved copy of the status register, and then execute
the eret instruction, as follows:
■
■
Before executing eret to change the register set, system software must set individual
external interrupt masks correctly to ensure that registers in the shadow register set
cannot be corrupted. If an interrupt is assigned to the register set, system software
must ensure that one of the following conditions is true:
■
■
Stacks and Shadow Register Sets
Depending on system requirements, the system software can create a dedicated stack
for each register set, or share a stack among several register sets. If a stack is shared,
the system software must copy the stack pointer each time the register set changes.
Use the rdprs instruction to copy the stack register between the current register set
and another register set.
If the processor is currently running in the normal register set, insert the new
register set number in estatus.CRS, and execute eret.
If the processor is currently running in a shadow register set, insert the new
register set number in sstatus.CRS, and execute eret.
The ISR is written to preserve register contents.
The individual interrupt is disabled. The method for disabling an individual
external interrupt is specific to the EIC implementation.
3–12.
Description
(1)
(1)
(1)
(1)
(1)
(1)
Table 3–35 on page
“Requested Register Set” on page
3–46.
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
December 2010 Altera Corporation
Chapter 3: Programming Model
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Reset
3–37. For details
Available
(1)
(1)
(1)
(1)
(1)
(1)
Registers