IPR-NIOS Altera, IPR-NIOS Datasheet - Page 42

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–20
Nios II Processor Reference Handbook
Table 2–6
are based on either the instruction or data bus. Trigger conditions on the same bus can
be logically ANDed, enabling the JTAG debug module to trigger, for example, only on
write cycles to a specific address.
Table 2–6. Trigger Conditions
When a trigger condition occurs during processor execution, the JTAG debug module
triggers an action, such as halting execution, or starting trace capture.
the trigger actions supported by the Nios II JTAG debug module.
Table 2–7. Trigger Actions
Armed Triggers
The JTAG debug module provides a two-level trigger capability, called armed
triggers. Armed triggers enable the JTAG debug module to trigger on event B, only
after event A. In this example, event A causes a trigger action that enables the trigger
for event B.
Triggering on Ranges of Values
The JTAG debug module can trigger on ranges of data or address values on the data
bus. This mechanism uses two hardware triggers together to create a trigger condition
that activates on a range of values within a specified range.
Specific address
Specific data value
Read cycle
Write cycle
Armed
Range
Break
External trigger
Trace on
Trace off
Trace sample
Arm
Notes to
(1) Only conditions on the data bus can trigger this action.
Condition
Action
Table
lists all the conditions that can cause a trigger. Hardware trigger conditions
2–7:
(1)
Data,
Instruction
Data
Data
Data
Data,
Instruction
Data
Halt execution and transfer control to the JTAG debug module.
Assert a trigger signal output. This trigger output can be used, for example,
to trigger an external logic analyzer.
Turn on trace collection.
Turn off trace collection.
Store one sample of the bus to trace buffer.
Enable an armed trigger.
Bus
Trigger when the bus accesses a specific address.
Trigger when a specific data value appears on the bus.
Trigger on a read bus cycle.
Trigger on a write bus cycle.
Trigger only after an armed trigger event. Refer to
Triggers” on page
Trigger on a range of address values, data values, or both. Refer
to
“Triggering on Ranges of Values” on page
2–20.
Description
Description
December 2010 Altera Corporation
Chapter 2: Processor Architecture
2–20.
Table 2–7
JTAG Debug Module
“Armed
lists