IPR-NIOS Altera, IPR-NIOS Datasheet - Page 61

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–10. bstatus Control Register Fields
December 2010 Altera Corporation
31
30
29
Reserved
28
1
1
27
26
The bstatus Register
The bstatus register holds a saved copy of the status register during break exception
processing.
All fields in the bstatus register have read/write access. All fields reset to 0.
Table 3–8
When a break occurs, the value of the status register is copied into bstatus. Using
bstatus, the debugger can restore the status register to the value prior to the break.
The bret instruction causes the processor to copy bstatus back to status. Refer to
“Processing a Break” on page 3–35
The ienable Register
The ienable register controls the handling of internal hardware interrupts. Each bit of
the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A
value of one in bit n means that the corresponding irqn interrupt is enabled; a bit
value of zero means that the corresponding interrupt is disabled. Refer to
Processing” on page 3–30
When the internal interrupt controller is not implemented, the value of the ienable
register is always 0.
The ipending Register
The value of the ipending register indicates the value of the interrupt signals driven
into the processor. A value of one in bit n means that the corresponding irqn input is
asserted. Writing a value to the ipending register has no effect.
The ipending register is present only when the internal interrupt controller is
implemented.
The cpuid Register
The cpuid register holds a constant value that uniquely identifies each processor in a
multiprocessor system. The cpuid value is determined at system generation time and
is guaranteed to be unique for each processor in the system. Writing to the cpuid
register has no effect.
The exception Register
When the extra exception information option is enabled, the Nios II processor
provides information useful to system software for exception processing in the
exception and badaddr registers when an exception occurs. When your system
contains an MMU or MPU, the extra exception information is always enabled. When
no MMU or MPU is present, the Nios II Processor parameter editor gives you the
option to have the processor provide the extra exception information.
25
24
23
describes the details of the fields defined in the bstatus register.
22
Table 3–10
21
20
19
PRS
shows the layout of the bstatus register.
18
for more information.
17
16
15
for more information.
14
13
CRS
12
11
10
9
8
Nios II Processor Reference Handbook
7
IL
6
5
4
3
“Exception
2
1
3–15
0