IPR-NIOS Altera, IPR-NIOS Datasheet - Page 64

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–18
Table 3–17. tlbmisc Control Register Fields
Table 3–18. tlbmisc Control Register Field Descriptions
Nios II Processor Reference Handbook
31
Notes to
(1) This field size is variable. Unused upper bits must be written as zero.
WAY
RD
WE
PID
DBL
BAD
PERM
D
Notes to
(1) You can also use exception.CAUSE to determine these exceptions.
30
Field
(1)
(1)
(1)
29
Table
Table
Reserved
28
3–17:
3–18:
The WAY field controls the mapping from the VPN to a particular TLB
entry.
RD is the read flag. Setting RD to one triggers a TLB read operation.
WE is the TLB write enable flag. When WE = 1, a write to tlbacc
writes through to a TLB entry.
PID is the process identifier field.
DBL is the double TLB miss exception flag.
BAD is the bad virtual address exception flag.
PERM is the TLB permission violation exception flag.
D is the data access exception flag. When D = 1, the exception is a
data access exception. When D = 0, the exception is an instruction
access exception.
27
26
The tlbacc register format is the recommended format for entries in the operating
system page table. The IG bits are ignored by the hardware on wrctl to tlbacc and
read back as zero on rdctl from tlbacc. The operating system can use the IG bits to
hold operating system specific information without having to clear these bits to zero
on a TLB write operation.
The tlbmisc Register
The tlbmisc register contains the remaining TLB-related fields and is only available in
systems with an MMU.
Table 3–18
The following sections provide further details of the tlbmisc fields.
The RD Flag
System software triggers a TLB read operation by setting tlbmisc.RD (with a wrctl
instruction). A TLB read operation loads the following register fields with the
contents of a TLB entry:
■
25
The tag portion of pteaddr.VPN
24
23
WAY
22
gives details of the fields defined in the tlbmisc register.
21
(1)
20
Description
19
18
Table 3–17
17
16
15
shows the layout of the tlbmisc register.
14
13
12
PID
11
10
(1)
Read/Write
Read/Write
Read/Write
9
Access
Write
Read
Read
Read
Read
8
December 2010 Altera Corporation
7
Chapter 3: Programming Model
6
Reset
5
0
0
0
0
0
0
0
0
4
3
Available
Only with
Only with
Only with
Only with
Only with
Only with
Only with
Only with
MMU
MMU
MMU
MMU
MMU
MMU
MMU
MMU
2
Registers
1
D
0