IPR-NIOS Altera, IPR-NIOS Datasheet - Page 127

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Custom Instructions Page
December 2010 Altera Corporation
Interrupt Vector Custom Instruction
Floating-Point Hardware Custom Instruction
f
1
1
The Nios II processor offers an interrupt vector custom instruction which reduces
average and worst case interrupt latency.
To add the interrupt vector custom instruction to the Nios II processor, select
Interrupt Vector from the list, and click Add.
There can only be one interrupt vector custom instruction component in a Nios II
processor. If the interrupt vector custom instruction is present in the Nios II processor,
the hardware abstraction layer (HAL) source detects it at compile time and generates
code using the custom instruction.
The interrupt vector custom instruction improves both average and worst case
interrupt latency by up to 20%. To achieve the lowest possible interrupt latency,
consider using tightly-coupled memories so that interrupt handlers can run without
cache misses.
The interrupt vector custom instruction is not compatible with the EIC interface. For
the Nios II/f core, the EIC interface with the Altera vectored interrupt controller
component provides superior performance.
For details of the interrupt vector custom instruction implementation, refer to
“Exception and Interrupt Controller” in the
Processor Reference Handbook. For guidance with tightly-coupled memories, refer to
“Tightly-Coupled Memory” in the
Reference Handbook.
The Nios II processor offers a set of optional predefined custom instructions that
implement floating-point arithmetic operations. You can include these custom
instructions to support computation-intensive floating-point applications.
The basic set of floating-point custom instructions includes single precision (32-bit)
floating-point addition, subtraction, and multiplication. Floating-point division is
available as an extension to the basic instruction set. The best choice for your
hardware design depends on a balance among floating-point usage, hardware
resource usage, and performance.
If the target device includes on-chip multiplier blocks, the floating-point custom
instructions incorporate them as needed. If there are no on-chip multiplier blocks, the
floating-point custom instructions are entirely based on general-purpose logic
elements.
The opcode extensions for the floating-point custom instructions are 252 through 255
(0xFC through 0xFF). These opcode extensions cannot be modified.
Processor Architecture
Processor Architecture
chapter of the Nios II Processor
Nios II Processor Reference Handbook
chapter of the Nios II
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