IPR-NIOS Altera, IPR-NIOS Datasheet - Page 89

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
Other Exceptions
Exception Processing Flow
f
1
The general exception handler can inspect the exception.CAUSE field to determine
which permissions were violated.
The data cache management instructions (initd, initda, flushd, and flushda) ignore
the TLB permissions and do not generate TLB permission violation exceptions.
MPU Region Violation
MPU region violation exceptions are implemented only in Nios II processors that
include the MPU. An MPU region violation exception is generated under any of the
following conditions:
■
■
The general exception handler reads the MPU region attributes to determine if the
address did not match any region or which permissions were violated.
There are two kinds of MPU region violation exceptions:
■
■
The general exception handler can inspect the exception.CAUSE field to determine
which kind of MPU region violation exception occurred.
The preceding sections describe all of the exception types defined by the Nios II
architecture at the time of publishing. However, some processor implementations
might generate exceptions that do not fall into the categories listed in the preceding
sections. Therefore, a robust exception handler must provide a safe response (such as
issuing a warning) in the event that it cannot identify the cause of an exception.
Except for the break exception (refer to
section describes how the processor responds to exceptions, including interrupts and
instruction-related exceptions.
For a detailed discussion of writing programs to take advantage of exception and
interrupt handling, refer to the
Developer’s Handbook.
An instruction fetch or data address matched a region but the permissions for that
region did not allow the action to complete.
An instruction fetch or data address did not match any region.
MPU region violation (instruction)—Any instruction fetch can cause this
exception.
MPU region violation (data)—Load, store, initda, and flushda instructions can
cause this exception.
Exception Handling
“Processing a Break” on page
chapter of the Nios II Software
Nios II Processor Reference Handbook
3–35), this
3–43