IPR-NIOS Altera, IPR-NIOS Datasheet - Page 281

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
stw / stwio
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
24
24
B
B
Mem32[rA + σ (IMM16)] ← rB
stw rB, byte_offset(rA)
stwio rB, byte_offset(rA)
stw r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Stores rB to the memory location specified by the effective byte
address. The effective byte address must be word aligned. If the byte address is not a multiple
of 4, the operation is undefined.
In processors with a data cache, this instruction may not generate an Avalon-MM data transfer
immediately. Use the stwio instruction for peripheral I/O. In processors with a data cache,
stwio bypasses the cache and is guaranteed to generate an Avalon-MM bus cycle. In
processors without a data cache, stwio acts like stw.
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
23
22
22
21
21
20
20
19
19
Instruction format for stwio
Instruction format for stw
18
18
17
17
16
16
15
15
IMM16
IMM16
14
14
store word to memory or I/O peripheral
13
13
12
12
11
11
10
10
9
9
8
8
Nios II Processor Reference Handbook
7
7
6
6
5
5
4
4
0x15
0x35
3
3
2
2
1
1
8–95
0
0