IPR-NIOS Altera, IPR-NIOS Datasheet - Page 235
IPR-NIOS
Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-NIOS.pdf
(294 pages)
Specifications of IPR-NIOS
License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 235 of 294
- Download datasheet (3Mb)
Chapter 8: Instruction Set Reference
Instruction Set Reference
divu
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
B
rC ← rA ÷ rB
divu rC, rA, rB
divu r6, r7, r8
Treating rA and rB as unsigned integers, this instruction divides rA by rB and then stores the
integer portion of the resulting quotient to rC. After attempted division by zero, the value of rC
is undefined. There is no divide-by-zero exception.
Nios II processors that do not implement the divu instruction cause an unimplemented
instruction exception.
Remainder of Division:
If the result of the division is defined, then the remainder can be computed in rD using the
following instruction sequence:
divu rC, rA, rB
mul rD, rC, rB
sub rD, rA, rD
Division error
Unimplemented instruction
R
A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
23
22
21
20
19
C
18
17
# The original divu operation
# rD = remainder
16
15
14
0x24
13
12
11
10
9
0
8
Nios II Processor Reference Handbook
7
6
divide unsigned
5
4
0x3a
3
2
1
8–49
0
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