MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 111

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.5 External Clock Operation Timing
10.6 Phase Locked Loop Timing
Freescale Semiconductor
Preliminary
1. Parameters listed are guaranteed by design.
2. See
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
Frequency of operation (external clock driver)
Frequency of operation (external clock driver)
Clock Pulse Width
External clock input rise time
External clock input fall time
External reference crystal frequency for the PLL
PLL output frequency
PLL output frequency
PLL stabilization time
correctly. The PLL is optimized for 8MHz input crystal.
56F8300 Peripheral User Manual.
Figure 10-3
External
Note: The midpoint is V
Clock
for details on using the recommended connection of an external clock driver.
Table 10-13 External Clock Operation Timing Requirements
3
3
2
2
Characteristic
Characteristic
(f
-40° to +125°C
(f
10%
OUT
OUT
50%
90%
5
)—56F8122
)—56F8322
4
t
PW
IL
+ (V
Figure 10-3 External Clock Timing
IH
– V
IL
56F8322 Technical Data, Rev. 16
Table 10-14 PLL Timing
2
2
)/2.
—56F8322
—56F8122
1
t
PW
Symbol
Symbol
f
f
t
t
t
PW
rise
osc
osc
fall
f
t
f
f
osc
plls
op
op
OUT
t
fall
/2), please refer to the OCCS chapter in the
Min
3.0
—
—
Min
160
160
0
0
—
4
Typ
Typ
—
—
—
—
—
—
—
8
1
External Clock Operation Timing
t
rise
Max
1
260
160
8.4
Max
10
120
80
15
15
—
10%
50%
90%
V
V
IH
IL
MHz
MHz
MHz
Unit
MHz
Unit
MHz
ms
ns
ns
ns
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