MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 55

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.2
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
5.3.3
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
Freescale Semiconductor
Preliminary
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
Interrupt Nesting
Fast Interrupt Handling
1. Core status register bits indicating current interrupt mask within the core.
SR[9]
1. See IPIC field definition in
0
0
1
1
IPIC_LEVEL[1:0]
1
Table 5-2. Interrupt Priority Encoding
Table 5-1 Interrupt Mask Bit Definition
00
01
10
11
SR[8]
56F8322 Technical Data, Rev. 16
1
0
1
0
1
1
No Interrupt or SWILP
Priority 0
Priority 1
Priorities 2 or 3
Section 5.6.30.2
Current Interrupt
Priority Level
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Permitted Exceptions
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Exception Priority
Required Nested
None
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
Masked Exceptions
Functional Description
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