MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 80

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2 Features
The SIM has the following features:
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
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Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory
Power-saving clock gating for peripherals
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart)
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
Controls to enable/disable the 56800E core WAIT and STOP instructions
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
Reset Mode, which has two submodes:
— Total Reset Mode
— Core-Only Reset Mode
Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation.
Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and
PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor
from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
56800E, memory and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped.
For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before
entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated
interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
– 56800E Core and all peripherals are reset
– 56800E Core in reset, peripherals are active
– This mode is required to provide the on-chip Flash interface module time to load data from Flash
into FM registers
56F8322 Techncial Data, Rev. 16
Freescale Semiconductor
Preliminary