MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 33

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note: Program RAM is NOT available on the 56F8122 device.
4.3 Interrupt Vector Table
Table 4-3
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see
Section 5.6.11
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWM, CAN and Quadrature Decoder are NOT available on the 56F8122 device.
Freescale Semiconductor
Preliminary
core
core
core
core
Peripheral
provides the device’s reset and interrupt priority structure, including on-chip peripherals. The
2
3
4
5
for the reset value of the VBA.
Number
Vector
P: $1F FFFF
P: $03 0000
P: $02 FFFF
P: $02 F800
P: $02 F7FF
P: $02 1000
P: $02 0FFF
P: $02 0000
P: $01 FFFF
P: $00 4000
P: $00 3FFF
P: $00 0000
Begin/End Address
3
3
3
3
Priority
Table 4-3 Interrupt Vector Table Contents
Level
Table 4-2 Program Memory Map at Reset
P:$04
P:$06
P:$08
P:$0A
Vector Base
Address +
56F8322 Technical Data, Rev. 16
RESERVED
On-Chip Program RAM
4KB
RESERVED
Boot Flash
8KB
Cop Reset Address = $02 0002
Boot Location = $02 0000
RESERVED
Internal Program Flash
32KB
Reserved for Reset Overlay
Reserved for COP Reset Overlay
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
Memory Allocation
Interrupt Function
2
1
2
Interrupt Vector Table
33