MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 81

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4 Operating Mode Register
The reset state for the MB bit will depend on the Flash secured state. See
detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device.
The EX bit is not functional in this device since there is no external memory interface. For all other bits,
see the 56F8300 Peripheral User Manual.
Note:
6.5 Register Descriptions
Freescale Semiconductor
Preliminary
RESET
Type
Bit
Address Offset
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
R/W
15
NL
0
14
0
13
0
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
SIM_CLKOSR
SIM_GPS
SIM_PCE
SIM_ISALH
SIM_ISALL
Address Acronym
12
0
11
0
56F8322 Technical Data, Rev. 16
Table 6-1 SIM Registers
(SIM_BASE = $00 F350)
10
Figure 6-1 OMR
0
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Pull-up Disable Register
Reserved
CLKO Select Register
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
9
0
R/W
CM
8
0
Register Name
R/W
XP
7
0
R/W
SD
6
0
R/W
5
R
0
R/W
SA
4
0
Section 4.2
R/W
EX
3
0
Section Location
Operating Mode Register
2
0
0
6.5.10
6.5.10
6.5.1
6.5.2
6.5.3
6.5.3
6.5.3
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
and
R/W
MB
1
X
Part 7
R/W
MA
0
0
for
81