MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 133

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3 Power Distribution and I/O Ring Implementation
Figure 12-1
contains two internal power regulators. One of them is powered from the V
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V
peripherals and the internal memories. This regulator can be turned off, if an external V
is externally applied to the V
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
Freescale Semiconductor
Preliminary
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•
•
•
•
•
OCS
V
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
Take special care to minimize noise levels on the V
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
Flash, RAM and internal logic are powered from the core regulator output
V
All circuitry, analog and digital, shares a common V
DDA_OSC_PLL
PP
1 and V
illustrates the general power control incorporated in the 56F8322/56F8122. This chip
DD
and V
PP
REG
2 are not connected in the customer system
DD_IO
SS
circuits.
ROSC
CAP
pins and provides power to all of the internal digital logic of the core, all
pins.
Figure 12-1 Power Management
56F8322 Technical Data, Rev. 16
REG
V
DD
CORE
REF
SS
V
SS
, V
V
bus
CAP
DDA
and V
I/O
Power Distribution and I/O Ring Implementation
SSA
pins
DDA_OSC_PLL
V
V
SSA_ADC
ADC
DDA_ADC
DD_CORE
pin and cannot
V
V
V
V
V
REFH
REFP
REFMID
REFN
REFLO
voltage
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