MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet - Page 112

• Manufacturer Part Number: MC56F8345VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8345VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.6.14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. This path has been optimized in order to
minimize any delay and clock duty cycle distortion. All other clocks primarily muxed out are for test
purposes only, and are subject to significant phase shift at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, [A23:A20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between [A23:A20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
[A23:A20]. This can be changed by altering [A23:A20], as shown in
6.5.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
6.5.7.3
6.5.7.4
6.5.7.5
112
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•
•
•
•
•
•
•
Base + $A
RESET
0 = Peripheral output function of GPIOB[7] is defined to be A[23]
1 = Peripheral output function of GPIOB[7] is defined to be the oscillator clock (MSTR_OSC, see
Figure
0 = Peripheral output function of GPIOB[6] is defined to be A[22]
1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2
0 = Peripheral output function of GPIOB[5] is defined to be A[21]
1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK
0 = Peripheral output function of GPIOB[4] is defined to be A[20]
1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see
Read
Write
CLKO Select Register (SIM_CLKOSR)
Reserved—Bit 2–0
Reserved—Bits 15–10
Alternate GPIO_B Peripheral Function for A23 (A23)—Bit 9
Alternate GPIO_B Peripheral Function for A22 (A22)—Bit 8
Alternate GPIO_B Peripheral Function for A21 (A21)—Bit 7
Alternate GPIO_B Peripheral Function for A20 (A20)—Bit 6
3-4)
15
0
0
14
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
13
0
0
12
0
0
56F8345 Technical Data, Rev. 17
11
0
0
10
0
0
A23
9
0
A22
8
0
A21
7
0
A20
6
0
Figure
CLK
DIS
5
1
6-9.
4
0
3
0
Freescale Semiconductor
CLKOSEL
2
0
Figure
1
0
Preliminary
3-4)
0
0