MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet - Page 141

• Manufacturer Part Number: MC56F8345VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8345VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.5 External Clock Operation Timing
10.6 Phase Locked Loop Timing
Freescale Semiconductor
Preliminary
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
1. Parameters listed are guaranteed by design.
2. See
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
Frequency of operation (external clock driver)
Clock Pulse Width
External clock input rise time
External clock input fall time
correctly. The PLL is optimized for 8MHz input crystal.
the 56F8300 Peripheral User Manual.
External
Note: The midpoint is V
Clock
Figure 10-3
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Characteristic
for details on using the recommended connection of an external clock driver.
3
10%
50%
90%
2
3
(f
-40° to +125°C
OUT
t
PW
IL
)
5
4
+ (V
Figure 10-3 External Clock Timing
IH
– V
IL
56F8345 Technical Data, Rev. 17
Table 10-14 PLL Timing
)/2.
2
t
PW
1
Symbol
f
t
t
Symbol
t
osc
PW
rise
fall
f
t
f
osc
plls
op
Min
3.0
—
—
0
Min
OUT
160
t
—
fall
4
/2), please refer to the OCCS chapter in
Typ
—
—
—
—
Typ
—
8
1
External Clock Operation Timing
t
rise
Max
Max
120
260
8.4
10
10
—
10
1
10%
50%
90%
MHz
V
V
Unit
MHz
MHz
Unit
ns
ns
ns
ms
IH
IL
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