MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 107

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.5.2 Real-Time Interrupt Flag Register
RTIF — Real-Time Interrupt Flag
10.5.3 COP Control Register
Read: Anytime
Write: Varies from bit to bit
CME — Clock Monitor Enable Bit
Write: Anytime
FCME — Force Clock Monitor Enable Bit
Write: Once in normal modes, anytime in special modes
Freescale Semiconductor
RTIF is set when the timeout period elapses. RTIF generates an interrupt request if the RTIE bit is set
in the RTI control register. Clear RTIF by writing to the real-time interrupt flag register with RTIF set.
CME enables the clock monitor. If the force clock monitor enable bit, FCME, is set, CME has no
meaning or effect.
FCME forces the clock monitor to be enabled until a reset occurs. When FCME is set, the CME bit has
no effect.
1 = Timeout period elapsed
0 = Timeout period not elapsed
1 = Clock monitor enabled
0 = Clock monitor disabled
1 = Clock monitor enabled
0 = CME bit enables or disables clock monitor
Address: $0015
Clear the CME bit before executing a STOP instruction and set the CME bit
after exiting stop mode.
Clear the FCME bit in applications that use the STOP instruction and the
clock monitor.
Address: $0016
Reset:
Read:
Write:
Reset:
Read:
Write:
Figure 10-8. Real-Time Interrupt Flag Register (RTIFLG)
RTIF
Bit 7
0
CME
Bit 7
0
Figure 10-9. COP Control Register (COPCTL)
= Unimplemented
FCME
6
0
0
6
0
MC68HC812A4 Data Sheet, Rev. 7
5
0
0
FCM
5
0
NOTE
NOTE
FCOP
4
0
0
4
0
3
0
0
DISR
3
0
2
0
0
CR2
2
0
Registers and Reset Initialization
1
0
0
CR1
1
0
Bit 0
0
0
Bit 0
CR0
0
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