MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 108

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Module
FCM — Force Clock Monitor Reset Bit
Write: Never in normal modes, anytime in special modes
FCOP — Force COP Reset Bit
Write: Never in normal modes; anytime in special modes
DISR — Disable Reset Bit
Write: Never in normal modes; anytime in special modes
CR2, CR1, and CR0 — COP Watchdog Timer Rate Select Bits
Write: Once in normal modes, anytime in special modes
108
FCM forces a reset when the clock monitor is enabled and detects a slow or stopped clock.
FCOP forces a reset when the COP is enabled and times out.
DISR disables clock monitor resets and COP resets.
The COP system is driven by a constant frequency of M/2
factor to arrive at the COP timeout rate. (The clock used for this module is the M-clock.)
1 = Clock monitor reset enabled
0 = Normal operation
1 = COP reset enabled
0 = Normal operation
1 = Clock monitor and COP resets disabled
0 = Normal operation
When the disable reset bit, DISR, is set, FCM has no effect.
When the disable reset bit, DISR, is set, FCOP has no effect.
CR[2:1:0]
000
001
010
011
100
101
110
111
Table 10-3. COP Watchdog Rates
M-Clock Divisor
MC68HC812A4 Data Sheet, Rev. 7
2
2
2
2
2
2
2
Off
13
15
17
19
21
22
23
NOTE
NOTE
0/+2.048 ms
M = 4.0 MHz
131.072 ms
524.288 ms
8.1920 ms
32.768 ms
2.048 ms
1.048 s
2.097 s
COP Timeout Period
Off
13
. These bits specify an additional division
0/+1.024 ms
M = 8.0 MHz
262.144 ms
524.288 ms
1.048576 s
16.384 ms
65.536 ms
1.024 ms
4.096 ms
Off
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