MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 191

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.7.4 SS (Slave Select)
The SS pin has multiple functions that depend on SPI configuration:
15.8 Low-Power Options
This section describes the three low-power modes:
15.8.1 Run Mode
Clearing the SPI enable bit, SPE, in SPI control register 1 reduces power consumption in run mode. SPI
registers are still accessible when SPE is cleared, but clocks to the core of the SPI are disabled.
15.8.2 Wait Mode
The SPI remains active in wait mode. Any enabled interrupt request from the SPI can bring the MCU out
of wait mode.
If SPI functions are not required during wait mode, reduce power consumption by disabling the SPI before
executing the WAIT instruction.
15.8.3 Stop Mode
For reduced power consumption, the SPI is inactive in stop mode. The STOP instruction does not affect
SPI register states. SPI operation resumes after an external interrupt.
Exiting stop mode by reset aborts any transmission in progress and resets the SPI. Entering stop mode
during a transmission results in invalid data.
Freescale Semiconductor
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The SS pin of a slave SPI is always configured as an input and allows the slave to be selected for
transmission.
When the CPHA bit is clear, the SS pin signals the start of a transmission.
The SS pin of a master SPI can be configured as a mode-fault input, a slave-select output, or a
general-purpose output.
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Run mode
Wait mode
Stop mode
As a mode-fault input (MSTR = 1, DDRS7 = 0, SSOE = 0), the SS pin can detect multiple
masters driving MOSI and SPSCK.
As a slave-select output (MSTR = 1, DDRS7 = 1, SSOE = 1), the SS pin can select slaves for
transmission.
When MSTR = 1, DDRS7 = 1, and SSOE = 0, the SS pin is available as a general-purpose
output.
MC68HC812A4 Data Sheet, Rev. 7
Low-Power Options
191