MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 39

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$00AC
$00AD
$00AE
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$00AF
$00B0
$00BF
$00C0
$00C1
Addr.
↓
↓
Pulse Accumulator Control
SCI 0 Baud Rate Register
SCI 0 Baud Rate Register
Timer Channel 7 Register
Timer Port Data Direction
Timer Port Data Register
Pulse Accumulator Flag
Counter Register High
Counter Register Low
Register Name
Timer Test Register
Pulse Accumulator
Pulse Accumulator
Register (PAFLG)
Register (PACTL)
Register (DDRT)
High (SC0BDH)
Low (SC0BDL)
See page 133.
See page 134.
See page 135.
See page 136.
See page 136.
See page 137.
See page 139.
See page 140.
See page 168.
See page 168.
Low (TC7L)
(PACNTH)
(PACNTL)
Reserved
Reserved
(TIMTST)
Reserved
Reserved
(PORTT)
↓
↓
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 2-1. Register Map (Sheet 11 of 14)
Bit 15
BTST
SBR7
Bit 7
Bit 7
Bit 0
Bit 7
Bit 7
PT7
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
MC68HC812A4 Data Sheet, Rev. 7
= Unimplemented
PAEN
SBR6
Bit 14
BSPL
Bit 6
Bit 6
Bit 6
PT6
R
R
R
R
6
0
0
0
0
0
0
0
0
0
0
0
PAMOD
BRLD
SBR5
Bit 13
Bit 5
Bit 5
Bit 5
PT5
R
R
R
R
5
0
0
0
0
0
0
0
0
0
0
0
PEDGE
SBR12
Unaffected by reset
Bit 12
SBR4
Bit 4
Bit 4
Bit 4
PT4
R
R
R
R
R
0
4
0
0
0
0
0
0
0
0
0
0
= Reserved
SBR11
Bit 11
SBR3
CLK1
Bit 3
Bit 3
Bit 3
PT3
R
R
R
R
3
0
0
0
0
0
0
0
0
0
0
0
SBR10
Bit 10
SBR2
CLK0
Bit 2
Bit 2
Bit 2
PT2
R
R
R
R
2
0
0
0
0
0
0
0
0
0
0
1
U = Unaffected
PAOVF
TCBYP
PAOVI
SBR9
SBR1
Bit 1
Bit 9
Bit 1
Bit 1
PT1
R
R
R
R
1
0
0
0
0
0
0
0
0
0
Register Map
PCBYP
SBR8
SBR0
Bit 0
PAIF
Bit 0
Bit 8
Bit 0
Bit 0
PT0
PAI
R
R
R
R
0
0
0
0
0
0
0
0
0
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