MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 136

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Standard Timer Module
PAIF — Pulse Accumulator Input Flag
12.5.16 Pulse Accumulator Counter Registers
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on the PAI pin since the last reset.
Use a double-byte read instruction to read the pulse accumulator counter. Two single-byte reads return
a different value than a double-byte read.
136
PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge
sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets
PAIF. Clear PAIF by writing to the pulse accumulator flag register with PAIF set.
1 = Active PAI input
0 = No active PAI input
Address: $00A2
Address: $00A3
When the fast flag clear-all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in the PAFLG
register.
Reading the pulse accumulator counter registers immediately after an
active edge on the PAI pin may miss the last count since the input has to
be synchronized with the bus clock first.
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit 15
Bit 7
Bit 7
Bit 7
0
0
Figure 12-23. Pulse Accumulator Counter
Bit 14
Bit 6
6
0
6
0
MC68HC812A4 Data Sheet, Rev. 7
Registers (PACNTH/L)
Bit 13
Bit 5
5
0
5
0
NOTE
NOTE
Bit 12
Bit 4
4
0
4
0
Bit 11
Bit 3
3
0
3
0
Bit 10
Bit 2
2
0
2
0
Bit 9
Bit 1
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
0
0