MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 202

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ATD)
PRS[4:0] — Prescaler Select Bits
16.6.6 ATD Control Register 5
Read: Anytime
Write: Anytime
S8CM — Select Eight Conversions Mode Bit
SCAN — Continuous Channel Scan Bit
202
The prescaler divides the P-clock by the binary value written to PRS[4:0] plus one. To assure
symmetry of the prescaler output, an additional divide-by-two circuit generates the ATD module clock.
Clearing PRS[4:0] means the P-clock is divided only by the divide-by-two circuit.
The reset state of PRS[4:0] is 00001, giving a total P-clock divisor of four, which is appropriate for
nominal operation at 2 MHz.
each P clock divisor.
S8CM selects conversion sequences of either eight or four conversions.
SCAN selects a single conversion sequence or continuous conversion sequences.
1 = Eight conversion sequences
0 = Four conversion sequences
1 = Continuous conversion sequences (scan mode)
0 = Single conversion sequence
Address: $0065
Reset:
Read:
1. Maximum conversion frequency is 2 MHz. Maximum P-clock divisor value becomes
2. Minimum conversion frequency is 500 kHz. Minimum P-clock divisor value becomes
Write:
PRS[4:0]
maximum conversion rate that can be used on this ATD module.
minimum conversion rate that this ATD can perform.
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
Bit 7
0
0
Figure 16-8. ATD Control Register 5 (ATDCTL5)
= Unimplemented
S8CM
Table 16-3
P-Clock
Divisor
6
0
Table 16-3. Clock Prescaler Values
10
12
14
16
2
4
6
8
MC68HC812A4 Data Sheet, Rev. 7
SCAN
5
0
shows the appropriate range of system clock frequencies for
Max P-Clock
MULT
4
0
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
Do not use
(1)
CD
3
0
CC
2
0
Min P-Clock
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
CB
1
0
(2)
Freescale Semiconductor
Bit 0
CA
0