MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 170

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Communications Interface Module (SCI)
M — Mode Bit
WAKE — Wakeup Bit
ILT — Idle Line Type Bit
PE — Parity Enable Bit
PT — Parity Type Bit
170
1. DDRSx means the data direction bit of the TXD pin.
LOOPS
M determines whether data characters are eight or nine bits long.
WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant
bit position of a received data character or an idle condition on the RXD pin.
ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins
either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
PE enables the parity function. When enabled, the parity function inserts a parity bit in the most
significant bit position.
PT determines whether the SCI generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity,
an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
1
1
1
1 = One start bit, nine data bits, one stop bit
0 = One start bit, eight data bits, one stop bit
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit.
0 = Idle character bit count begins after start bit.
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
RSRC
1
1
1
DDRSx
0
1
1
Table 14-7. Loop Mode Functions (Continued)
(1)
WOMS
MC68HC812A4 Data Sheet, Rev. 7
x
0
1
Single-wire mode; transmitter output disconnected
TXD is high-impedance receiver input
Single-wire mode; TXD pin connected to receiver input
Single wire mode; TXD pin connected to receiver input
TXD is open-drain for receiving and transmitting
Function of TXD Pin
Freescale Semiconductor