MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 57

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

commands can be executed while the CPU is operating normally. Other BDM commands are firmware
based and require the BDM firmware to be enabled and active for execution.
In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all
other operating modes, but must be enabled before it can be activated. BDM should not be used in special
peripheral mode because of potential bus conflicts.
Once enabled, background mode can be made active by a serial command sent via the BKGD pin or
execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special
debugging commands, and read and write CPU registers, peripheral registers, and locations in memory.
While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses
$FF20 to $FFFF, and BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM
replaces the regular system vectors while BDM is active. While BDM is active, the user memory from
$FF00 to $FFFF is not in the map except through serial BDM commands.
5.3 Internal Resource Mapping
The internal register block, RAM, and EEPROM have default locations within the 64-Kbyte standard
address space but may be reassigned to other locations during program execution by setting bits in
mapping registers INITRG, INITRM, and INITEE. During normal operating modes, these registers can be
written once. It is advisable to explicitly establish these resource locations during the initialization phase
of program execution, even if default values are chosen, to protect the registers from inadvertent
modification later.
Writes to the mapping registers go into effect between the cycle that follows the write and the cycle after
that. To assure that there are no unintended operations, a write to one of these registers should be
followed with a NOP (no operation) instruction.
If conflicts occur when mapping resources, the register block takes precedence over the other resources;
RAM or EEPROM addresses occupied by the register block are not available for storage. When active,
BDM ROM takes precedence over other resources although a conflict between BDM ROM and register
space is not possible.
All address space not used by internal resources is external memory by default.
The memory expansion module manages three memory overlay windows:
The sizes and locations of the program and data overlay windows are fixed. One of two locations can be
selected for the extra page (EPAGE).
Freescale Semiconductor
1. Program
2. Data
3. One extra page overlay
Table 5-2
Precedence
shows resource mapping precedence.
1
2
3
4
5
Table 5-2. Mapping Precedence
MC68HC812A4 Data Sheet, Rev. 7
BDM ROM (if active)
External memory
Register space
Resource
EEPROM
RAM
Internal Resource Mapping
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