MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 190

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface (SPI)
15.6.5 SPI Data Register
Read: Anytime; normally, only after SPIF flag set
Write: Anytime a data transfer is not taking place
The SPI data register is both the input and output register for SPI data. Reads are double-buffered but
writes cause data to be written directly into the SPI shift register. The data registers of two SPIs can be
connected through their MOSI and MISO pins to form a distributed 16-bit register. A transmission between
the SPIs shifts the data eight bit positions, exchanging the data between the master and the slave. The
slave can also be another simpler device that only receives data from the master or that only sends data
to the master.
15.7 External Pins
The SPI module has four I/O pins:
The SPI has limited inter-integrated circuit (I
single-master environment. To communicate with I
when the SWOM bit in the SPI control register is set. In I
connected to a bidirectional pin from the I
15.7.1 MISO (Master In, Slave Out)
In a master SPI, MISO is the data input. In a slave SPI, MISO is the data output.
In a slave SPI, the MISO output pin is enabled only when its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin of a slave puts the MISO pin in a high-impedance state.
15.7.2 MOSI (Master Out, Slave In)
In a master SPI, MOSI is the data output. In a slave SPI, MOSI is the data input.
15.7.3 SCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master SPI, the
SCK pin is the clock output to the slave. In a slave MCU, the SCK pin is the clock input from the master.
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MISO — Master data in, slave data out
MOSI — Master data out, slave data in
SCK — Serial clock
SS — Slave select
Address: $00D5
Reset:
Read:
Write:
Bit 7
Bit 7
Figure 15-13. SPI Data Register (SP0DR)
6
6
MC68HC812A4 Data Sheet, Rev. 7
2
5
5
C peripheral and through a pullup resistor to V
2
C) capability (requiring software support) as a master in a
Unaffected by reset
2
4
4
C peripherals, MOSI becomes an open-drain output
2
C communication, the MOSI and MISO pins are
3
3
2
2
1
1
Freescale Semiconductor
Bit 0
Bit 0
DD
.