MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 63

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 6
Bus Control and Input/Output (I/O)
6.1 Introduction
Internally the MCU has full 16-bit data paths, but depending upon the operating mode and control
registers, the external bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit accesses can
appear on adjacent cycles using the LSTRB signal to indicate 8-bit or 16-bit data.
6.2 Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking
place. Accesses to the internal RAM module are the only type of access that produce LSTRB = A0 = 1,
because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle.
In these cases, the data for the address that was accessed is on the low half of the data bus and the data
for address +1 is on the high half of the data bus.
6.3 Registers
Not all registers are visible in the memory map under certain conditions. In special peripheral mode, the
first 16 registers associated with bus expansion are removed from the memory map.
In expanded modes, some or all of port A, port B, port C, port D, and port E are used for expansion buses
and control signals. To allow emulation of the single-chip functions of these ports, some of these registers
must be rebuilt in an external port replacement unit. In any expanded mode, port A, port B, and port C are
used for address and data lines so registers for these ports, as well as the data direction registers for
these ports, are removed from the on-chip memory map and become external accesses.
Freescale Semiconductor
LSTRB
1
0
1
0
0
1
0
1
Table 6-1. Access Type versus Bus Control Pins
A0
0
1
0
1
0
1
0
1
MC68HC812A4 Data Sheet, Rev. 7
R/W
1
1
0
0
1
1
0
0
16-bit write to an even address
16-bit write to an even address
16-bit read of an even address
8-bit read of an even address
8-bit write of an even address
16-bit read of an odd address
8-bit write of an odd address
8-bit read of an odd address
(low/high data swapped)
(low/high data swapped)
Type of Access
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