MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 93

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 9
Key Wakeups
9.1 Introduction
The key wakeup feature of the MC68HC812A4 issues an interrupt that wakes up the CPU when it is in
stop or wait mode. Three ports are associated with the key wakeup function: port D, port H, and port J.
Port D and port H wakeups are triggered with a falling signal edge. Port J key wakeups have a selectable
falling or rising signal edge as the active edge. For each pin which has an interrupt enabled, there is a
path to the interrupt request signal which has no clocked devices when the part is in stop mode. This
allows an active edge to bring the part out of stop.
Default register addresses, as established after reset, are indicated in the following descriptions. For
information on remapping the register block, refer to
9.2 Key Wakeup Registers
This section provides a summary of the key wakeup registers.
9.2.1 Port D Data Register
This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE
register bit EMD set.
An interrupt is generated when a bit in the KWIFD register and its corresponding KWIED bit are both set.
These bits correspond to the pins of port D. All eight bits/pins share the same interrupt vector and can
wake the CPU when it is in stop or wait mode. Key wakeups can be used with the pins configured as
inputs or outputs.
Key wakeup port D shares a vector and control bit with IRQ. IRQEN must be set for key wakeup interrupts
to signal the CPU.
Freescale Semiconductor
Alternate pin function:
Address: $0005
Reset:
Read:
Write:
KWD7
Bit 7
PD7
0
Figure 9-1. Port D Data Register (PORTD)
KWD6
PD6
MC68HC812A4 Data Sheet, Rev. 7
6
0
KWD5
PD5
5
0
Chapter 5 Operating Modes and Resource
KWD4
PD4
4
0
KWD3
PD3
3
0
KWD2
PD2
2
0
KWD1
PD1
1
0
KWD0
Bit 0
PD0
0
Mapping.
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