MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 138

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Standard Timer Module
12.6.2 Pulse Accumulator Pin
Setting the PAE bit in the pulse accumulator control register enables the pulse accumulator input pin, PAI.
12.7 Background Debug Mode
If the TSBCK bit is clear, background debug mode has no effect on the timer. If TSBCK is set, background
debug mode disables the timer.
12.8 Low-Power Options
This section describes the three low-power modes:
12.8.1 Run Mode
Clearing the timer enable bit (TEN) or the pulse accumulator enable bit (PAEN) reduces power
consumption in run mode. TEN is in the timer system control register (TSCR). PAEN is in the pulse
accumulator control register (PACTL). Timer and pulse accumulator registers are still accessible, but
clocks to the core of the timer are disabled.
12.8.2 Wait Mode
Timer and pulse accumulator operation in wait mode depend on the state of the TSWAI bit in the timer
system control register TSCR).
12.8.3 Stop Mode
The STOP instruction disables the timer for reduced power consumption.
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Run mode
Wait mode
Stop mode
If TSWAI is clear, the timer and pulse accumulator operate normally when the CPU is in wait mode.
If TSWAI is set, timer and pulse accumulator clock generation ceases and the TIM module enters
a power-conservation state when the CPU is in wait mode. In this condition, timer and pulse
accumulator registers are not accessible. Setting TSWAI does not affect the state of the timer
enable bit, TEN, or the pulse accumulator enable bit, PAEN.
The PAI input and timer channel 7 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 7 output mode
and output level bits, OM7 and OL7. Also clear the channel 7 output
compare mask bit, OC7M7.
Setting TSBCK does not stop the pulse accumulator when it is in event
counter mode.
MC68HC812A4 Data Sheet, Rev. 7
NOTE
NOTE
Freescale Semiconductor