MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 54

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
4.7 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared.
When an interrupt request is recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles required to complete the instruction.
Some of the longer instructions can be interrupted and resume normally after servicing the interrupt.
When the CPU begins to service an interrupt request, it:
After stacking the CCR, the CPU:
If no other interrupt request is pending at the end of the interrupt service routine, an RTI instruction
recovers the stacked values. Program execution resumes program at the return address.
If another interrupt request is pending at the end of an interrupt service routine, the RTI instruction
recovers the stacked values. However, the CPU then:
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Clears the instruction queue
Calculates the return address
Stacks the return address and the contents of the CPU registers as shown in
Sets the I bit to prevent other interrupts from disrupting the interrupt service routine
Sets the X bit if an XIRQ interrupt request is pending
Fetches the interrupt vector for the highest-priority request that was pending at the beginning of the
interrupt sequence
Begins execution of the interrupt service routine at the location pointed to by the vector
Adjusts the stack pointer to point again at the stacked CCR location, SP – 9
Fetches the vector of the pending interrupt
Begins execution of the interrupt service routine at the location pointed to by the vector
Table 4-2. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
MC68HC812A4 Data Sheet, Rev. 7
Stacked Values
RTN
Y
X
B : A
CCR
H
H
H
: RTN
: Y
: X
L
L
L
Freescale Semiconductor
Table 4-2