MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 3

IC MCU 16BIT EEPROM 4K 112-LQFP

MC812A4CPVE8

Manufacturer Part Number
MC812A4CPVE8
Description
IC MCU 16BIT EEPROM 4K 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC812A4CPVE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
83
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC812A
Core
HC12
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
91
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Controller Family/series
68HC12
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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MC68HC812A4
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Freescale Semiconductor
(Continued
http://freescale.com
August,
on next
page)
2001
Date
Revision
Level
4
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic — Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic — Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
Figure 8-16. Chip-Select Control Register 0 (CSCTL0) — Corrected reset
value for CSPOE (bit 5)
Figure 10-1. Clock Module Block Diagram — Corrected E- and P-clock
generator options
Figure 11-1. PLL Block Diagram — Revised diagram to show correct
placement of divide-by-two block
12.11.2 Timer Port Data Direction Register — Descriptive paragraph added
for clarity
MC68HC812A4 Data Sheet, Rev. 7
Description
Number(s)
Page
138
156
170
209
40
42
3

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