MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 203

IC MCU 16BIT EEPROM 4K 112-LQFP

MC812A4CPVE8

Manufacturer Part Number
MC812A4CPVE8
Description
IC MCU 16BIT EEPROM 4K 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC812A4CPVE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
83
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC812A
Core
HC12
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
91
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Controller Family/series
68HC12
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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MULT — Multichannel Conversion Bit
CD, CC, CB, and CA — Channel Select Bits
Freescale Semiconductor
Refer to
The channel select bits select the input to convert. LT = 1, the ATD sequencer selects
1 = Conversions of sequential channels
0 = Conversions of a single input channel selected by the CD, CC, CB, and CA bits
Table
1. When MULT = 1, bits with asterisks are don’t care bits. The 4-conversion sequence from
S8CM
AN0 to AN3 or the 8-conversion sequence from AN0 to AN7 is completed in the order
shown.
When MULT = 0, the CD, CC, CB, and CA bits select one input channel. The conversion
sequence is performed on this channel only.
0
0
1
1
16-4.
Table 16-4. Multichannel Mode Result Register Assignment
CD
0
1
0
1
CC
0*
1*
0*
1*
0
1
0
1
CB
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
0*
0*
1*
1*
MC68HC812A4 Data Sheet, Rev. 7
CA
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
0*
1*
Channel Input
Test/Reserved
Test/Reserved
(V
(V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RH
RH
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
V
V
V
V
+ V
+ V
RH
RH
RL
RL
RL
RL
)/2
)/2
Result in ADRxH
Registers and Reset Initialization
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH4
ADRxH5
ADRxH6
ADRxH7
ADRxH0
ADRxH1
ADRxH2
ADRxH3
ADRxH4
ADRxH5
ADRxH6
ADRxH7
(1)
203

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