MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 19

IC MCU 64K FLASH EEPROM 80-TQFP

MC9S12NE64VTUE

Manufacturer Part Number
MC9S12NE64VTUE
Description
IC MCU 64K FLASH EEPROM 80-TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12NE64VTUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Processor Series
S12N
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
125 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12NE64E, DEMO9S12NE64E
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Total Internal Ram Size
8KB
# I/os (max)
70
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.625/3.465V
Operating Supply Voltage (min)
2.357/2.375/3.135V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
TQFP
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12NE64VTUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12NE64VTUE
Manufacturer:
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Chapter 1
MC9S12NE64 Device Overview
1.1
The MC9S12NE64 is a 112-/80-pin cost-effective, low-end connectivity applications MCU family. The
MC9S12NE64 is composed of standard on-chip peripherals including a 16-bit central processing unit
(HCS12 CPU), 64K bytes of FLASH EEPROM, 8K bytes of RAM, Ethernet media access controller
(EMAC) with integrated 10/100 Mbps Ethernet physical transceiver (EPHY), two asynchronous serial
communications interface modules (SCI), a serial peripheral interface (SPI), one inter-IC bus (IIC), a
4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ATD), up to 21 pins
available as keypad wakeup inputs (KWU), and two additional external asynchronous interrupts. The
inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational
requirements. Furthermore, an on-chip bandgap-based voltage regulator (VREG_PHY) generates the
internal digital supply voltage of 2.5 V (VDD) from a 3.15 V to 3.45 V external supply range. The
MC9S12NE64 has full 16-bit data paths throughout. The 112-pin package version has a total of 70 I/O port
pins and 10 input-only pins available. The 80-pin package version has a total of 38 I/O port pins and 10
input-only pins available.
1.1.1
Freescale Semiconductor
16-bit HCS12 core
— HCS12 CPU
— Memory map and interface (MMC)
— Interrupt control (INT)
— Background debug mode (BDM)
— Enhanced debug12 module, including breakpoints and change-of-flow trace buffer (DBG)
— Multiplexed expansion bus interface (MEBI) — available only in 112-pin package version
Wakeup interrupt inputs
— Up to 21 port bits available for wakeup interrupt function with digital filtering
Memory
— 64K bytes of FLASH EEPROM
— 8K bytes of RAM
Analog-to-digital converter (ATD)
— One 8-channel module with 10-bit resolution
— External conversion trigger capability
Introduction
Features
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to M68HC11
– Instruction queue
– Enhanced indexed addressing
MC9S12NE64 Data Sheet, Rev 1.0
19

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