MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 488

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 18 Debug Module (DBGV1)
18.3.2.10 Debug Comparator A Register (DBGCA)
18.3.2.11 Debug Comparator B Extended Register (DBGCBX)
488
EXTCMP
PAGSEL
Reset
Reset
Reset
Field
Field
15:0
15:0
7:6
5:0
W
W
W
R
R
R
Bit 15
Bit 7
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
15
0
0
0
7
7
Table 18-11
PAGSEL
18-11.
Figure 18-19. Debug Comparator B Extended Register (DBGCBX)
Figure 18-17. Debug Comparator A Register High (DBGCAH)
Figure 18-18. Debug Comparator A Register Low (DBGCAL)
Bit 14
Bit 6
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see
14
0
0
0
6
6
Table 18-22. DBGCBX Field Descriptions
Table 18-21. DBGCA Field Descriptions
Bit 13
Bit 5
MC9S12NE64 Data Sheet, Rev. 1.1
13
0
0
0
5
5
Bit 12
Bit 4
12
0
0
0
4
4
Description
Description
Table
18-20.
Bit 11
Bit 3
11
0
0
0
3
3
EXTCMP
Bit 10
Bit 2
10
0
0
0
2
2
Freescale Semiconductor
Bit 9
Bit 1
0
0
0
9
1
1
Table
Bit 8
Bit 0
0
0
0
8
0
0
18-20.