MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 339

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.3.2 Deferring
In half-duplex mode, if there is a carrier (the network is busy), the network node continues to listen until
the carrier ceases (network is idle). This is known as deferring to the passing traffic. As soon as the network
becomes idle (which includes waiting for the interframe gap interval), the network node may begin
transmitting a frame. The transmitter waits for the carrier sense to be negated for 60 bit times and then
begins transmit after another 36 bit times.
11.4.3.3 Collision Detection and Backoff
The collision detection and backoff feature is a normal part of the operation of Ethernet 802.3 MAC
protocol, and results in fast and automatic rescheduling of transmissions. This feature enables independent
network nodes to compete for network access in a fair manner. It provides a way for network nodes to
automatically adjust their behavior in response to the load of the network.
11.4.3.3.1
The collision window period is set to 64 byte times (512 bit times) starting after the SFD. If a collision
occurs within the collision window period, the retry process is initiated. If a late collision occurs (that is,
a collision after the collision window period), no retransmission is performed, the LCIF bit sets to 1, the
transmit retry counter is cleared, and transmission is aborted. If not masked (LCIE is set), the EMAC
generates a late collision interrupt. Due to latency associated with synchronizing the MII_COL signal,
assertions in the last three MII_TXCLK cycles of a normally completed transmission (during the FCS) are
ignored and a collision event is not recognized.
11.4.3.3.2
If a collision is detected anytime during transmission, the EMAC transmitter continues to transmit 32 bits
of data (called the collision enforcement jam signal) so that other devices on the Ethernet network,
including the offending transmitter, can detect the collision. If the collision is detected very early in the
frame transmission, the EMAC transmitter continues sending until it has completed the preamble of the
frame, after which it sends the 32 bits of jam data. If the collision is detected during the FCS, up to and
including the transfer of the last nibble of FCS data, the 32 bit jam is still sent.
11.4.3.3.3
After a collision occurs within the collision window period, the delay time that the EMAC transmitter
waits before attempting to retransmit the frame data is set at a multiple of the 512-bit Ethernet slot time.
The amount of total backoff delay is calculated by multiplying the slot time by a pseudo-randomly chosen
integer.
The backoff algorithm uses the following formula to determine the integer r, which is used to multiply the
slot time and generate a backoff delay.
Freescale Semiconductor
Collision Window
Jam Period
Backoff Generator
MC9S12NE64 Data Sheet, Rev. 1.1
0 r
≤
<
2
k
Functional Description
339