MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 372

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
A 2.5 MHz internal clock is used for nibble wide transactions. A 10 MHz internal clock is used for serial
transactions.
Parallel to Serial: Converts the 4-bit wide nibbles from the MII to serial format before the information is
processed by subsequent blocks.
Manchester Encoder: Allows encoding of both the clock and data in one bit stream. A logical one is
encoded as a zero when the clock is high and a one when the clock is low. A logical zero is encoded as a
one when the clock is high and a zero when the clock is low.
Digital Filter: Performs pre-emphasis and low pass filtering of the input Manchester data.
DAC: Converts the digital data to an analog format before transmission on the media.
Carrier Sense: In half-duplex operation, carrier is asserted when either the transmit or receive medium is
active. In full-duplex operation, carrier asserted only on reception of data. During receive, carrier sense is
asserted during reception of a valid preamble, and de-asserted after reception of an EOF.
Loopback: Enabled when bit 0.14 is asserted. This loopback mode allows for the Manchester encoded and
filtered data to be looped back to the squelch block in the receive path. All the 10BASE-T digital functions
are exercised during this mode. The transmit and receive channels are disconnected from the media.
MII loopback (18.13) must be disabled to allow for correct operation of the digital loopback (0.14).
Link Generator: Generates a 100 ns duration pulse at the end of every 12 ms period of the transmission
path being idle (TXEN de-asserted). This pulse is used to keep the 10BASE-T link operational in the
absence of data transmission.
372
TX
RX
MII
MII
PARALLEL
PARALLEL
SERIAL
SERIAL
TO
TO
CARRIER
SENSE
MANCHESTER
RECOVERY
DECODER
Figure 12-21. 10BASE-T Block Diagram
MANCHESTER
TIMING
ENCODER
AND
MC9S12NE64 Data Sheet, Rev. 1.1
JABBER
POLARITY
CHECK
DIGITAL
FILTER
SQUELCH
LOOPBACK
(bit 0.14)
DIGITAL
LINE TRANSMITTER/
LINE RECEIVER
Freescale Semiconductor
PHY_RXN
PHY_TXN
PHY_TXP
PHY_RXP