MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 487

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.2.9
1
2
Freescale Semiconductor
DBG
BKP
EXTCMP
See
See
comparators A and B in DBG mode only).
PAGSEL
Reset
Field
7:6
5:0
1
2
Figure
Figure 18-10
W
R
Not FLASH/ROM access
18-16.
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively).
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator A Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
FLASH/ROM access
Debug Comparator A Extended Register (DBGCAX)
NOTES:
1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state).
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
0
7
Table 18-20
Mode
PORTK/XAB
PAGSEL = 00
PAGSEL = 01
PAGSEL
(note that while this figure provides extended comparisons for comparator C, the figure also pertains to
Figure 18-16. Comparators A and B Extended Comparison in BKP Mode
18-20.
DBGCXX
PPAGE
Figure 18-15. Debug Comparator A Extended Register (DBGCAX)
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
0
6
XAB21
PIX7
SEE NOTE 1
SEE NOTE 2
0
PAGSEL
Table 18-20. Comparator A or B Compares
Table 18-19. DBGCAX Field Descriptions
XAB20
PIX6
0
MC9S12NE64 Data Sheet, Rev. 1.1
0
5
EXTCMP[5:0] = XAB[19:14]
EXTCMP[5:0] = XAB[21:16]
EXTCMP Compare
XAB19
PIX5
5
No compare
No compare
0
4
XAB18
PIX4
4
Description
XAB17
PIX3
3
EXTCMP
0
3
EXTCMP
XAB16
PIX2
2
DBGCxH[7:0] = XAB[15:14], AB[13:8]
XAB15
0
2
PIX1
DBGCxH[7:0] = AB[15:8]
DBGCxH[5:0] = AB[13:8]
DBGCxH[7:0] = AB[15:8]
1
Memory Map and Register Definition
High-Byte Compare
XAB14
BIT 0
PIX0
0
1
0
0
487